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searching for Translation lookaside buffer 4 found (76 total)

alternate case: translation lookaside buffer

ARM Cortex-A72 (436 words) [view diff] exact match in snippet view article find links to article

configurable size per cluster 48-entry fully associative L1 instruction translation lookaside buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes

ARM Cortex-A57 (477 words) [view diff] case mismatch in snippet view article find links to article

configurable size per cluster 48-entry fully associative L1 instruction Translation Lookaside Buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes

TurboSPARC (709 words) [view diff] exact match in snippet view article find links to article

lines. The SBus controller had its own 16-entry input/output translation lookaside buffer. TurboSPARC supported SBus frequencies of 16.67 to 25 MHz. The

Scientific Research Institute of System Development (842 words) [view diff] exact match in snippet view article find links to article

addresses into 36-bit physical ones; ·64-address (128-page) virtual translation lookaside buffer (jTLB); ·separate virtual address translation buffer (micro TLB)