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Longer titles found: Macrocell array (view)

searching for Macrocell 17 found (37 total)

alternate case: macrocell

GAL22V10 (739 words) [view diff] exact match in snippet view article find links to article

mode, each macrocell actively uses a D-flip-flop to hold a state under control of the data input from the logic portion of the macrocell and the rising

MICTOR (174 words) [view diff] exact match in snippet view article find links to article

trace signals like ARM CoreSight ETM (Embedded Trace Macrocell) or PTM (Program Trace Macrocell). The minimal variant of MICTOR consists of 38 signal

ARM Cortex-A57 (477 words) [view diff] exact match in snippet view article find links to article

little impact on performance. TrustZone security extensions Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution

ARM Cortex-A72 (436 words) [view diff] exact match in snippet view article find links to article

little impact on performance. TrustZone security extensions Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution

Simple programmable logic device (323 words) [view diff] exact match in snippet view article find links to article

7400-series TTL. They typically comprise 4 to 22 fully connected macrocells. These macrocells typically consist of some combinatorial logic (such as AND OR

Lin Yi-bing (1,520 words) [view diff] exact match in snippet view article find links to article

Lin, P., & Lin, Y. (2013). Reducing Signaling Overhead for Femtocell/Macrocell Networks. IEEE Transactions on Mobile Computing. Sanchez-Esguevillas,

ARM Cortex-A9 (1,031 words) [view diff] exact match in snippet view article find links to article

support for Java execution. Jazelle RCT for JIT compilation. Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution

ARM Cortex-A15 (1,366 words) [view diff] exact match in snippet view article find links to article

TrustZone security extensions Jazelle RCT for JIT compilation Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution

JTAG (7,041 words) [view diff] exact match in snippet view article find links to article

halt the core being debugged. Some toolchains can use ARM Embedded Trace Macrocell (ETM) modules, or equivalent implementations in other architectures to

ESilicon (864 words) [view diff] exact match in snippet view article find links to article

cards for eSilicon next year". 2006-10-24. "eSilicon unveils "HardCore" macrocell program". 2007-06-18. Archived from the original on 2013-01-21. "eSilicon

MIPI Debug Architecture (2,400 words) [view diff] exact match in snippet view article find links to article

module to merge with further trace streams. ARM's CoreSight System Trace Macrocell, which is compliant with MIPI STP, is today an integral part of most multi-core

Cell site (3,465 words) [view diff] exact match in snippet view article find links to article

station tower: it is technically possible to cover up to 50–150 km. (Macrocell) 5G (FR2) Mobile base station: the distances between the 5G base-station

Telecommunications lease (1,830 words) [view diff] exact match in snippet view article find links to article

populated urban areas where multiple 5G nodes or small cells could render a macrocell site obsolete with emphasis placed on cell sites with higher rental payments

ARM Cortex-M (5,908 words) [view diff] exact match in snippet view article find links to article

Memory Protection Unit (MPU): 8 or 16 regions. Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data. Optional Retention Mode

Roberto Morandotti (1,346 words) [view diff] exact match in snippet view article find links to article

Ozaki, T.; Morandotti, R. (2013). "Enhanced Q-factor in Optimally Coupled Macrocell THz Metamaterials: Effect of Spatial Arrangement". IEEE Journal of Selected

MOSAID (1,920 words) [view diff] exact match in snippet view article find links to article

MOSAID entered the SIP (Semiconductor IP) market to provide silicon-proven macrocell blocks to system-on-chip developers. The first product was a DDR3 SDRAM

ARM architecture family (13,724 words) [view diff] exact match in snippet view article find links to article

SoC-400, CoreSight SDC-600, CoreSight STM-500, CoreSight System Trace Macrocell, CoreSight Trace Memory Controller Design Kits: Corstone-101, Corstone-201