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Longer titles found: Quil (instruction set architecture) (view), Language for Instruction Set Architecture (view), Comparison of instruction set architectures (view)

searching for Instruction set architecture 79 found (461 total)

alternate case: instruction set architecture

Soft microprocessor (432 words) [view diff] exact match in snippet view article find links to article

support Notes Project home Description language based on the ARM instruction set architecture Amber Conor Santifort LGPLv2.1 Wishbone ARMv2a 3-stage or 5-stage

Virtual address space (739 words) [view diff] exact match in snippet view article find links to article

can extend to the highest address allowed by the computer's instruction set architecture and supported by the operating system's pointer size implementation

AIM alliance (2,134 words) [view diff] exact match in snippet view article find links to article

industry-wide open-standard computing platform based on the POWER instruction set architecture.: 69 It was intended to solve legacy problems, future-proof

Java bytecode (1,732 words) [view diff] no match in snippet view article find links to article

Java bytecode is the instruction set of the Java virtual machine (JVM), the language to which Java and other JVM-compatible source code is compiled. Each

R4200 (985 words) [view diff] exact match in snippet view article find links to article

designed by MIPS Technologies that implemented the MIPS III instruction set architecture and was initially referred to as the VRX during development.

MIL-STD-1750A (1,257 words) [view diff] exact match in snippet view article find links to article

MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer instruction set architecture (ISA), including both required and optional components, as described

Interdata (602 words) [view diff] exact match in snippet view article find links to article

32-bit minicomputers that were loosely based on the IBM 360 instruction set architecture but at a cheaper price. In 1974, it produced one of the first

Code morphing (309 words) [view diff] exact match in snippet view article find links to article

processors such as the Crusoe and Efficeon to implement the x86 instruction set architecture. Code morphing is often used in obfuscating the copy protection

UNCOL (494 words) [view diff] exact match in snippet view article find links to article

intended to make compilers economically available for each new instruction set architecture and programming language, thereby reducing an N×M problem to

EnCore Processor (503 words) [view diff] exact match in snippet view article find links to article

configurable and extendable implementation of a compact 32-bit RISC instruction set architecture - developed by the PASTA Research Group at the University of

Link register (655 words) [view diff] exact match in snippet view article find links to article

general-purpose register, so that register is designated by the instruction set architecture as the link register. The ARMv7 architecture uses general-purpose

Advanced Computing Environment (2,141 words) [view diff] exact match in snippet view article find links to article

the successor to personal computers based on Intel's 32-bit instruction set architecture. The effort found little support in the market and dissolved

Latency oriented processor architecture (1,607 words) [view diff] no match in snippet view article find links to article

Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This

List of former IA-32 compatible processor manufacturers (949 words) [view diff] exact match in snippet view article find links to article

to build microprocessors that are compatible with that Intel instruction set architecture. Most of these companies were not successful in the mainstream

PC12 minicomputer (483 words) [view diff] exact match in snippet view article find links to article

at the Artronix facility in suburban St. Louis, Missouri. The instruction set architecture was adapted from the LINC, the only significant change was to

CDC 6600 (6,282 words) [view diff] no match in snippet view article find links to article

The CDC 6600 was the flagship of the 6000 series of mainframe computer systems manufactured by Control Data Corporation. Generally considered to be the

Altera (1,350 words) [view diff] exact match in snippet view article find links to article

the Nios V embedded soft processor cores based on the RISC-V instruction set architecture. Previously Altera had offered their own proprietary Nios II

Formal equivalence checking (1,131 words) [view diff] exact match in snippet view article find links to article

equivalence checking to compare the functions specified for the instruction set architecture (ISA) with a register transfer level (RTL) implementation, ensuring

Breakpoint (1,237 words) [view diff] exact match in snippet view article find links to article

(typically instruction and data breakpoints). As an example, the x86 instruction set architecture provides hardware support for breakpoints with its x86 debug

IBM System/360 Model 65 (597 words) [view diff] no match in snippet view article find links to article

The Model 65 implements the complete System/360 "universal instruction set" architecture, including floating-point, decimal, and character operations

Apache Mynewt (882 words) [view diff] case mismatch in snippet view article find links to article

micro:bit (Nordic nrf51822; Cortex-M0) SiFive HiFive1 (RISC-V Instruction Set Architecture) NINA-B1 BLE module from u-blox (Cortex-M4) 6LoWPAN clicker from

Ingenic Semiconductor (851 words) [view diff] exact match in snippet view article find links to article

XBurst CPU technology consists of 2 parts: A RISC/SIMD/DSP hybrid instruction set architecture which enables the processor to have the capability of computation

IBM System/360 Model 75 (344 words) [view diff] no match in snippet view article find links to article

The Model 75 implements the complete System/360 "universal instruction set" architecture, including floating-point, decimal, and character operations

Intel Galileo (1,438 words) [view diff] exact match in snippet view article find links to article

is a 32-bit, single core, single-thread, Pentium (P54C/i586) instruction set architecture (ISA)-compatible CPU, operating at speeds up to 400 MHz. The

Deepin (1,889 words) [view diff] exact match in snippet view article find links to article

RISC-V hardware and software "to be recognized as a mainstream instruction set architecture" by 2036. Starting with the release of Version 23 in August 2024

Neural processing unit (4,926 words) [view diff] exact match in snippet view article find links to article

evolving at a dramatic speed, DLPs start to leverage dedicated ISA (instruction set architecture) to support the deep learning domain flexibly. At first, DianNao

Krishna Palem (2,153 words) [view diff] case mismatch in snippet view article find links to article

an application specific and therefore a Dynamically VAriable Instruction SeT Architecture (DVAITA). The Analysts' Choice Awards recognized this technology

Glossary of reconfigurable computing (1,051 words) [view diff] exact match in snippet view article find links to article

Hybrid-core computing is the technique of extending a commodity instruction set architecture (e.g. x86) with application-specific instructions to accelerate

RV (disambiguation) (389 words) [view diff] exact match in snippet view article

disease among infants and young children RISC-V, an open standard instruction set architecture RV, or recreational vehicle Re-entry vehicle, a space vehicle

Cheetah (disambiguation) (515 words) [view diff] exact match in snippet view article

version codenamed "Cheetah" Cheetah, a forerunner of the IBM POWER instruction set architecture Cheetah, a hard drive made by Seagate Technology Cheetah, a robot

Mac 68k emulator (800 words) [view diff] exact match in snippet view article find links to article

contained a special trap instruction and flags indicating the instruction set architecture (ISA) of the called code. From PowerPC code, this UPP could be

ESA (disambiguation) (462 words) [view diff] exact match in snippet view article

semantic analysis IBM Enterprise Systems Architecture, a mainframe instruction set architecture Sonex Electric Sport Aircraft, an electric aircraft Enhanced

Alpha (disambiguation) (1,228 words) [view diff] exact match in snippet view article

AlphaStation, DEC now HP workstation successor to the VAX DEC Alpha, an instruction set architecture developed by Digital Equipment Corporation (DEC) Wolfram Alpha

MIPS Technologies (3,852 words) [view diff] exact match in snippet view article find links to article

cores. The MIPS32 architecture is a high-performance 32-bit instruction set architecture (ISA) that is used in applications such as 32-bit microcontrollers

HyperScan (932 words) [view diff] exact match in snippet view article find links to article

microarchitecture designed by Sunplus Technology. The S+core instruction set architecture has a 32/16-bit hybrid instruction mode, features Advanced Microcontroller

IBM 2922 (461 words) [view diff] exact match in snippet view article find links to article

The 2922-1 Terminal Control Unit (RPQ 810563) has the same instruction set architecture as the Model 20. It incorporates 8,192 bytes of 3.6 μs magnetic-core

IBM System/360 Model 50 (1,402 words) [view diff] no match in snippet view article find links to article

The Model 50 implements the complete System/360 "universal instruction set" architecture, including floating-point, decimal, and character operations

PDP-6 (1,975 words) [view diff] exact match in snippet view article find links to article

single word and read and write one in a single operation. The instruction set architecture could be categorized as "one-and-a-half address". The opcode

Intel i960 (2,502 words) [view diff] no match in snippet view article find links to article

the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design. In the Extended architecture, the memory subsystem

X87 (2,520 words) [view diff] exact match in snippet view article find links to article

Subset of x86 instruction set architecture for floating-point arithmetic

List of acronyms: I (3,355 words) [view diff] case mismatch in snippet view article find links to article

(i) Individual Savings Account Industry Standard Architecture Instruction Set Architecture International Seabed Authority ISAAA – (i) International Service

Bfloat16 floating-point format (1,800 words) [view diff] case mismatch in snippet view article find links to article

conversion is round to nearest even and overflow to inf. "Arm A64 Instruction Set Architecture". developer.arm.com. Retrieved 2023-07-26. Uses the non-IEEE

IBM System z10 (1,483 words) [view diff] exact match in snippet view article find links to article

in a built-in, integral component of each processor core and instruction set architecture. As examples, Enterprise PL/I, XL C, and the z/OS Java BigDecimal

Concurrency control (2,976 words) [view diff] exact match in snippet view article find links to article

Transactional Synchronization Extensions – Extension to the x86 instruction set architecture that adds hardware transactional memory support Database transaction

Tandem Computers (5,738 words) [view diff] exact match in snippet view article find links to article

its top-level modular architecture or its programming-level instruction set architecture. Within each series, there have been several major re-implementations

Ruby B. Lee (388 words) [view diff] exact match in snippet view article find links to article

architecture and innovations in the design and implementation of the instruction set architecture of RISC processors." She also became a Fellow of the Institute

Mach-O (5,331 words) [view diff] exact match in snippet view article find links to article

type indicates the instruction set architecture for the code. If the file is for the 64-bit version of the instruction set architecture, the CPU type value

Surface (2012 tablet) (1,376 words) [view diff] exact match in snippet view article

Store applications. Windows RT is compiled entirely for the ARM instruction set architecture. A major update to Windows RT was launched on October 17, 2013

Panasonic M2 (2,671 words) [view diff] exact match in snippet view article find links to article

– Dual 66 MHz PowerPC 602 Implements the 32-bit PowerPC RISC instruction set architecture PowerPC CPU designed for consumer electronics applications 1

ABA problem (1,429 words) [view diff] case mismatch in snippet view article find links to article

Multithreaded Primitives, reprinted from Overload #142, 2017 John Goodacre and Andrew N. Sloss. "Parallelism and the ARM Instruction Set Architecture". p. 46.

IBM 801 (2,703 words) [view diff] exact match in snippet view article find links to article

efficiently fabricated at various scales. The result was the IBM POWER instruction set architecture and the PowerPC offshoot. For his work on the 801, John Cocke

Python (programming language) (14,391 words) [view diff] no match in snippet view article

some libraries written in C. PyPy offers support for the RISC-V instruction-set architecture, for example. Codon is an implentation with an ahead-of-time

Linux Foundation (3,589 words) [view diff] exact match in snippet view article find links to article

association is chartered to standardize and promote the open RISC-V instruction set architecture together with its hardware and software ecosystem for use in

Uzi Vishkin (1,879 words) [view diff] exact match in snippet view article find links to article

ACM: Fellows Award / Uzi Vishkin. Vishkin, Uzi. Spawn-join instruction set architecture for providing explicit multithreading. U.S. Patent 6,463,527

Spinlock (1,733 words) [view diff] case mismatch in snippet view article find links to article

John Goodacre and Andrew N. Sloss. "Parallelism and the ARM Instruction Set Architecture". p. 47. Jonathan Corbet (9 December 2009). "Spinlock naming

ST6 and ST7 (965 words) [view diff] case mismatch in snippet view article find links to article

Microcontroller/Microprocessor directory, 8-bit microprocessors sorted by Instruction Set Architecture" (PDF). p. 26. 100616 edn.com "ST6 Family Programming Manual"

Radeon RX 6000 series (2,570 words) [view diff] case mismatch in snippet view article find links to article

Official website Comparative Chipset Specs Table - AMD Radeon RX 6950 XT, RX 6900 XT, RX 6800 XT, RX 6800 and RX 6750 XT RDNA 2 Instruction Set Architecture

Adreno (3,082 words) [view diff] exact match in snippet view article find links to article

Retrieved 13 June 2018. freedreno (6 January 2015). "A3xx shader instruction set architecture · freedreno/freedreno Wiki · GitHub". Github.com. Retrieved 5

Reverse computation (1,801 words) [view diff] exact match in snippet view article find links to article

at the hardware level, but included descriptions of both an instruction set architecture and a high level programming language (R) for a processor based

Elxsi (980 words) [view diff] exact match in snippet view article find links to article

from three large boards of ECL gate arrays. Key elements of its instruction set architecture were: 16 registers (64-bit) 32-bit linear address space (64-bit

Supercomputer (8,133 words) [view diff] exact match in snippet view article find links to article

Model – The computing platform as it is marketed. Processor – The instruction set architecture or processor microarchitecture, alongside GPU and accelerators

PDP-11 (6,811 words) [view diff] exact match in snippet view article find links to article

interface. T-11 is a microprocessor that implements the PDP-11 instruction set architecture. It was developed for embedded systems and was the first single-chip

PSE-36 (1,585 words) [view diff] case mismatch in snippet view article find links to article

Professional. p. 62. ISBN 978-0-13-028084-8. Tom Shanley (2009). x86 Instruction Set Architecture. MindShare Press. pp. 578–579. ISBN 9780977087853. Sajal Dam

Quadruple-precision floating-point format (3,081 words) [view diff] exact match in snippet view article find links to article

original (PDF) on 2005-02-04. Retrieved 2011-09-24. SPARC is an instruction set architecture (ISA) with 32-bit integer and 32-, 64-, and 128-bit IEEE Standard

Bare machine computing (1,475 words) [view diff] exact match in snippet view article find links to article

kernel. A given BMC application suite simply runs on a given instruction set architecture (ISA) for ever, as along the ISA remains upward compatible. This

Stanford University (19,140 words) [view diff] exact match in snippet view article find links to article

era were IBM's efforts that eventually led to the IBM POWER instruction set architecture, PowerPC, and Power ISA. As these projects matured, a wide variety

Afara Websystems (1,161 words) [view diff] exact match in snippet view article find links to article

further derivative UltraSPARC T3 (2010). While SPARC is an open instruction set architecture, where vendors build their own processors to an open specification

List of computing mascots (1,290 words) [view diff] exact match in snippet view article find links to article

compiler frontend for any programming language and backend for any instruction set architecture. A stylized wyvern Xenia An alternative mascot for Linux An anthropomorphic

Radeon RX Vega series (3,728 words) [view diff] case mismatch in snippet view article find links to article

Enhanced Performance and Power Efficiency". AMD. "Vega" 7nm Instruction Set Architecture Reference Guide Vega: AMD's New Graphics Architecture for Virtually

List of computing and IT abbreviations (6,587 words) [view diff] case mismatch in snippet view article find links to article

to Intermediate System ISA—Industry Standard Architecture ISA—Instruction Set Architecture ISAM—Indexed Sequential Access Method ISATAP—Intra-Site Automatic

ILLIAC IV (5,445 words) [view diff] exact match in snippet view article find links to article

was false. CU: control unit CPU: central processing unit ISA: instruction set architecture MAC: multiply-and-accumulate PC: program counter PE: processing

Explicit multi-threading (1,572 words) [view diff] exact match in snippet view article find links to article

1109/TPDS.2017.2754376, hdl:1903/18521. Vishkin, Uzi. Spawn-join instruction set architecture for providing explicit multithreading. U.S. Patent 6,463,527

HP 3000 (5,002 words) [view diff] case mismatch in snippet view article find links to article

word addressed, byte-addressable, segmented, Harvard, Stack Instruction Set Architecture (ISA). Most of the ~214 instructions are 16 bits wide. Stack

C syntax (10,497 words) [view diff] exact match in snippet view article find links to article

complex. This distinction reflects similar distinctions in the instruction set architecture of most central processing units. Integral data types store numbers

CDNA (microarchitecture) (1,957 words) [view diff] case mismatch in snippet view article

5, 2020. Retrieved September 22, 2022. ""AMD Instinct MI100" Instruction Set Architecture, Reference Guide" (PDF). developer.amd.com. December 14, 2020

Valentina Salapura (1,722 words) [view diff] no match in snippet view article find links to article

ISBN 3-540-58419-6. Salapura, Valentina (2011). "Vector Extensions, Instruction-Set Architecture (ISA)". In Padua, David A. (ed.). Encyclopedia of Parallel Computing

Acorn Archimedes (30,349 words) [view diff] exact match in snippet view article find links to article

that one might be added, with a floating-point co-processor instruction set architecture having been defined by Acorn for programs to use. As part of

Ark Compiler (890 words) [view diff] exact match in snippet view article find links to article

implementing platform related utilities. ISA function provides common instruction set architecture that is language-independent that allows to run HarmonyOS applications

Ridge Computers (4,508 words) [view diff] exact match in snippet view article find links to article

Cerberus multiprocessor simulator used a processor model with an instruction set architecture derived from that of the Ridge 32's CPU. At their peak, Ridge