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searching for Demand-based switching 7 found (9 total)

List of Intel Xeon processors (Core-based) (877 words) [view diff] case mismatch in snippet view article

L5238, L5240. E5205, L5238, L5240, X5260, X5270, X5272 support Demand-Based Switching. All models support dual-processor configurations Die size: 107 mm2

List of Intel Xeon processors (NetBurst-based) (780 words) [view diff] no match in snippet view article

models support dual-processor configurations Die size: 2× 81 mm² Demand Based Switching (Intel's Server EIST): Supported by: All except 5060, 5063. Die

List of Intel Xeon processors (Nehalem-based) (774 words) [view diff] case mismatch in snippet view article

All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Demand-Based Switching (Intel's Server EIST), Intel 64, XD bit (an NX bit implementation)

List of Intel Xeon processors (Yonah-based) (58 words) [view diff] no match in snippet view article

Pentium M microarchitecture All models support: MMX, SSE, SSE2, SSE3, Demand Based Switching (Intel's Server EIST), XD bit (an NX bit implementation), Intel

List of Intel Itanium processors (1,456 words) [view diff] no match in snippet view article find links to article

Advanced Machine Check Architecture, Cache Safe technology, Enhanced Demand Based Switching, ECC, two memory controllers each with two SMI links to memory buffers

Itanium (13,258 words) [view diff] exact match in snippet view article find links to article

nm process, it was changed into a fix of Montecito, enabling the demand-based switching (like EIST) and up to 667 MT/s front-side bus, which were intended

List of Intel CPU microarchitectures (2,899 words) [view diff] exact match in snippet view article find links to article

multithreading, and other improvements. The Montvale update added demand-based switching (SpeedStep) and core-level lockstep execution. Tukwila enhanced