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searching for Combinational logic 32 found (94 total)

And-inverter graph (1,069 words) [view diff] exact match in snippet view article find links to article

and verification to share the same data structure. In addition to combinational logic, AIGs have also been applied to sequential logic and sequential transformations

State encoding for low power (1,499 words) [view diff] exact match in snippet view article find links to article

combination of these. Combinational logic minimization uses unassigned state-codes as don't-care states in order to reduce the combinational logic. Following are

Algorithmic state machine (1,952 words) [view diff] exact match in snippet view article find links to article

register, a counter, or a register preceded by a combinational logic block. The combinational logic block associated with a register may implement an

Gating (telecommunication) (85 words) [view diff] exact match in snippet view article

specified amplitude limits. The controlling of signals by means of combinational logic elements. A process in which a predetermined set of conditions, when

Low-power FSM synthesis (870 words) [view diff] exact match in snippet view article find links to article

FSM will be easier to build State encoding: The complexity of the combinational logic depends on the assignment of codes to each of the states in the FSM

Aart de Geus (2,185 words) [view diff] exact match in snippet view article find links to article

that developed tools including the Synthesis and Optimization of Combinational logic, using a Rule-based and Technology-independent Expert System (SOCRATES)

MOSQUITO (1,170 words) [view diff] exact match in snippet view article find links to article

noting that the calculation of register bits is performed using combinational logic, and the shift, naturally, using register logic, which means that

Fault model (735 words) [view diff] case mismatch in snippet view article find links to article

Chang, Magdy S. Abadir, Sep Seyedi, "Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG"

Maurice Karnaugh (539 words) [view diff] case mismatch in snippet view article find links to article

1953) [1953-04-23, 1953-03-17]. "The Map Method for Synthesis of Combinational Logic Circuits" (PDF). Transactions of the American Institute of Electrical

Virtex (FPGA) (1,692 words) [view diff] exact match in snippet view article

four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions required by SoC designs, the percentage of combinational

Edward W. Veitch (883 words) [view diff] case mismatch in snippet view article find links to article

1953) [1953-04-23, 1953-03-17]. "The Map Method for Synthesis of Combinational Logic Circuits" (PDF). Transactions of the American Institute of Electrical

Transient Reactor Test Facility (2,800 words) [view diff] exact match in snippet view article find links to article

commercial plant RPS in several ways. First, a commercial plant RPS uses combinational logic (e.g. 2 out of 3, or 2 out of 4) of the protection system channels

Edward W. Veitch (883 words) [view diff] case mismatch in snippet view article find links to article

1953) [1953-04-23, 1953-03-17]. "The Map Method for Synthesis of Combinational Logic Circuits" (PDF). Transactions of the American Institute of Electrical

LEON (1,718 words) [view diff] exact match in snippet view article find links to article

to suppress effects from Single Event Transient (SET) errors in combinational logic. The LEON family includes the first LEON1 VHSIC Hardware Description

Random testing (1,396 words) [view diff] case mismatch in snippet view article find links to article

"Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks". IEEE Transactions on Computers. C-24 (7): 691–695. doi:10

XOR gate (2,695 words) [view diff] exact match in snippet view article find links to article

Press. ISBN 978-0-8493-0885-7. Retrieved 8 November 2022. Designing combinational logic gates in CMOS (PDF). p. 233. Retrieved 9 November 2022. Annaratone

Vishwani Agrawal (925 words) [view diff] case mismatch in snippet view article find links to article

"Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks". IEEE Transactions on Computers. C-24 (7): 691–695. doi:10

74181 (1,606 words) [view diff] exact match in snippet view article find links to article

The combinational logic circuitry of the 74181 integrated circuit

Euler diagram (3,634 words) [view diff] case mismatch in snippet view article find links to article

1953) [1953-04-23, 1953-03-17]. "The Map Method for Synthesis of Combinational Logic Circuits" (PDF). Transactions of the American Institute of Electrical

Turing machine equivalents (2,667 words) [view diff] exact match in snippet view article find links to article

Oblivious machines correspond in a step-wise linear fashion with combinational logic circuits, when the complexity of the transition table is taken as

Ring counter (2,297 words) [view diff] exact match in snippet view article find links to article

hardware implementations where registers are more expensive than combinational logic. Johnson counters are sometimes favored, because they offer twice

List of 4000-series integrated circuits (1,102 words) [view diff] exact match in snippet view article find links to article

there are numerous 4000-series parts, this section groups related combinational logic parts to make it easier for the reader to choose part numbers. All

Counter (digital) (5,202 words) [view diff] exact match in snippet view article

Typical architectures of digital counters Some counters employ combinational logic between state register and counter outputs to transform the state

Xilinx (9,168 words) [view diff] exact match in snippet view article find links to article

four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions required by SoC designs, the percentage of combinational

Karnaugh map (3,588 words) [view diff] case mismatch in snippet view article find links to article

1953) [1953-04-23, 1953-03-17]. "The Map Method for Synthesis of Combinational Logic Circuits" (PDF). Transactions of the American Institute of Electrical

Don't-care term (2,327 words) [view diff] case mismatch in snippet view article find links to article

1953) [1953-04-23, 1953-03-17]. "The Map Method for Synthesis of Combinational Logic Circuits" (PDF). Transactions of the American Institute of Electrical

Memristor (13,731 words) [view diff] exact match in snippet view article find links to article

doi:10.1049/el.2010.3407. Chattopadhyay, A.; Rakosi, Z. (2011). "Combinational logic synthesis for material implication". 2011 IEEE/IFIP 19th International

List of 7400-series integrated circuits (1,789 words) [view diff] exact match in snippet view article find links to article

easier to pick a useful part number. This section only includes combinational logic gates. For part numbers in this section, "x" is the 7400-series logic

Hack computer (4,251 words) [view diff] exact match in snippet view article find links to article

provides the computational functionality of the computer. The ALU is a combinational logic device having two 16-bit input operands and a single 16-bit output

List of fellows of IEEE Circuits and Systems Society (78 words) [view diff] exact match in snippet view article find links to article

Tsutomu Sasao For contributions to the design theory and techniques of combinational logic circuits. 1995 Periasamy Rajan For contributions to research and

List of fellows of IEEE Solid-State Circuits Society (81 words) [view diff] exact match in snippet view article find links to article

Tsutomu Sasao for contributions to the design theory and techniques of combinational logic circuits 1994 Robert Swartz for contributions to the design of high-speed

List of fellows of IEEE Computer Society (124 words) [view diff] exact match in snippet view article find links to article

Tsutomu Sasao For contributions to the design theory and techniques of combinational logic circuits. 2002 M Satyanarayanan For contributions to scalable and