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searching for RISC-V 18 found (142 total)

alternate case: rISC-V

LiteOS (303 words) [view diff] exact match in snippet view article find links to article

different architectures such as ARM (M0/3/4/7, A7/17/53, ARM9/11), x86, and RISC-V are supported by the project. Huawei LiteOS is part of Huawei's "1+2+1"
VxWorks (3,495 words) [view diff] exact match in snippet view article find links to article
supports AMD/Intel architecture, POWER architecture, ARM architectures and RISC-V. The RTOS can be used in multicore asymmetric multiprocessing (AMP), symmetric
Tsinghua Shenzhen International Graduate School (588 words) [view diff] exact match in snippet view article find links to article
two-dimensional materials and graphene research. RISC-V International Open Source Laboratory In November 2019, the RISC-V International Open Source Laboratory (RIOS
GigaDevice (411 words) [view diff] exact match in snippet view article find links to article
some of them are based on ARM architecture (GD32 series), and other on RISC-V architecture (GD32V series). GD32 chips were introduced in 2015 and are
Linux Foundation (6,608 words) [view diff] exact match in snippet view article find links to article
ground up for the realtime web." The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture together
Ancient UNIX (456 words) [view diff] exact match in snippet view article find links to article
teaching system, which is an update of that version to ANSI C and the x86 or RISC-V platform. As an example of how relicensing the old Unix code bases has affected
Carbon nanotube computer (341 words) [view diff] exact match in snippet view article find links to article
message: “Hello, world! I am RV16XNano, made from CNTs”. It is based on the RISC-V instruction set and runs standard 32-bit instructions on 16-bit data and
Comparison of boot loaders (161 words) [view diff] exact match in snippet view article find links to article
Blackfin, ColdFire, IXP, Leon2, m68k, MicroBlaze, MIPS, NIOS, NIOS2, PXA, x86, RISC-V, StrongARM, SH2, SH3, SH4, ... FAT12(RO), FAT16, FAT32, VFAT, ext2, ext3
Maxine Virtual Machine (848 words) [view diff] exact match in snippet view article find links to article
Java Operating system Solaris, Linux, macOS Platform x64, ARM32, AArch64, RISC-V Type Java virtual machine License GPL version 2.0 Website github.com/beehive-lab/Maxine-VM 
OpenPOWER Foundation (1,187 words) [view diff] exact match in snippet view article find links to article
keynote and OpenPOWER blows the doors off: Royalty-free, open soft-core (RISC-V sweating gallons) Chiselwatt's page on Github IBM (2020-06-27). "A2I on
AI accelerator (2,217 words) [view diff] exact match in snippet view article find links to article
general purpose vector accelerators are the way forward (in relation to RISC-V hwacha project. Argues that NN's are just dense and sparse matrices, one
Embench (362 words) [view diff] exact match in snippet view article find links to article
Cooperative (Towards the Long Overdue and Deserved Demise of Dhrystone) (PDF). "RISC-V Workship Zürich. ETH Zürich, Switzerland.CS1 maint: date format (link) McCarthy
Cache hierarchy (3,014 words) [view diff] exact match in snippet view article find links to article
A. Patterson; John L. Hennessy; 2017. Computer Organization and Design RISC-V Edition: The Hardware Software Interface. Elsevier Science. pp. 386–387
Photonically Optimized Embedded Microprocessors (151 words) [view diff] case mismatch in snippet view article find links to article
Computer Sciences DARPA , News and events Electricity, Light, Join Forces to Advance Computing Chen Sun RISC-­‐V Microprocessor Chip with Photonic I/O
Instruction set simulator (1,610 words) [view diff] exact match in snippet view article find links to article
Simulation And Tracing" Imperas provide an ISS for over 170 processor variants for ARM, ARMv8, MIPS, MIPS64, PowerPC, RISC-V, ARC, Nios-II, MicroBlaze ISAs.
Memory ordering (3,129 words) [view diff] exact match in snippet view article find links to article
WinChip manufactured around 1998) may have weaker 'oostore' memory ordering. RISC-V memory ordering models: WMO Weak memory order (default) TSO Total store
ZPU (microprocessor) (1,167 words) [view diff] exact match in snippet view article
ed.). Waltham, MA: Elsevier. ISBN 978-0-12-383872-8. Asanovic, Krste. "RISC-V: An Open Standard for SoCs". EE Times. Universal Business Media. Retrieved
Register allocation (5,060 words) [view diff] exact match in snippet view article find links to article
number of scalar registers in the most common architectures Architecture 32 bits 64 bits ARM 15 31 Intel x86 8 16 MIPS 32 32 RISC-V 16/32 32 SPARC 31 31