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searching for High-Logic 14 found (15 total)

alternate case: high-Logic

Pull-up resistor (695 words) [view diff] no match in snippet view article find links to article

brings the wire up to the high logic level. When another component on the line goes active, it will override the high logic level set by the pull-up resistor
Integrated injection logic (562 words) [view diff] no match in snippet view article find links to article
either a current sink (low logic level) or as a high-z floating condition (high logic level). The output of an inverter is at the collector. Likewise, it is
Static discipline (51 words) [view diff] no match in snippet view article find links to article
In a digital circuit or system, static discipline defines the "logic high", "logic low", VOH (output high), VOL (output low), VIH (input high) voltages
NMOS logic (639 words) [view diff] no match in snippet view article find links to article
example, here is a NOR gate in NMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance
Diode–transistor logic (912 words) [view diff] no match in snippet view article find links to article
common-emitter amplifier stage (Q1 and R2). If both inputs A and B are high (logic 1; near V+), then the diodes D1 and D2 are reverse biased. Resistors
Digital signal (633 words) [view diff] no match in snippet view article find links to article
levels represent the binary integers or logic levels of 0 and 1. In active-high logic, "low" represents binary 0 and "high" represents binary 1. Active-low
Differential signaling (1,276 words) [view diff] no match in snippet view article find links to article
why, consider a single-ended digital system with supply voltage . The high logic level is and the low logic level is 0 V. The difference between the two
XDR DRAM (1,880 words) [view diff] no match in snippet view article find links to article
SDO output connected to the controller, and the first SDI input tied high (logic 0). On reset, each chip drives its SDO pin low (1). When reset is released
NvSRAM (691 words) [view diff] no match in snippet view article find links to article
initiated when Vcc power down is detected Chip enable must be maintained at high logic to prevent inadvertent read/writes Static operation. Data is stored in
Universal asynchronous receiver/transmitter (2,762 words) [view diff] no match in snippet view article find links to article
stop transmitting to the device when the device drives the CTS# signal high (logic 0). 16750 64-byte buffers. This UART can handle a maximum standard serial
Font management software (865 words) [view diff] exact match in snippet view article find links to article
PostScript Type 1, raster, TrueType, vector MainType Windows Proprietary High-Logic OpenType, PostScript Type 1, raster, TrueType, vector MasterJuggler OS
MIDI 1.0 (1,803 words) [view diff] no match in snippet view article find links to article
High → no current flow → Opto-isolator LED off → MIDI receiver sees High, logic '1' (data bits, stop bit or idle) Logic 0 → Low → current loop flow →
Boolean algebra (8,902 words) [view diff] no match in snippet view article find links to article
input is represented by a voltage on the lead. For so-called "active-high" logic, 0 is represented by a voltage close to zero or "ground", while 1 is
Econet (2,521 words) [view diff] no match in snippet view article find links to article
cable was terminated at each end to prevent reflections and to guarantee high logic levels when the bus was undriven. The original connectors were five-pin